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| OSD PRESSOR FOR MONITOR (PRELIMINARY) S5D2509 PRODUCT SUMMARY INTRODUCTION S5D2509 is a stand-alone OSD Processor, which is used to display monitor adjustment or status information as a certain character or symbol on screen. Its basic operation includes making the R/ G/ B signal for the character or symbol by controlling the internal memory, synchronizing it with the horizontal flyback signal, and mixing it with the main video signal in the video AMP IC. The font data for making the character or symbol is stored in the internal ROM. It is accessed and controlled by the control data, transmitted from the micro controller through the I2C bus. The chip contains internal PLL circuitry, so all timing control signals, including the system clock, are synchronized with the horizontal flyback signal. FEATURES * * * * * * * * * * * * * * * * * * * * * * * * Enough font to support multiple language : 448 Standard Fonts + 16 Multi-Color Fonts Wide Operating (Horizontal) Frequency Range : 30kHz 120kHz Four Selectable OSD Resolutions : 640, 800, 1024 and 1280 Dots/ Line Pixel Frequency provided by On-Chip PLL : 19.2MHz 153.6MHz General Font Matrix : 12 x 18 Fully Programmable Display Area : 15 Rows x 30 Columns Popular MCU Interface : I2C Protocol Built in 1K-byte SRAM PWM DAC Channels with 8 Bit Resolution : 8EA Selectable Character Color (Up to 16 Color) : Font basis Selectable Raster Color (Up to 16 Color) : Font basis Programmable and Auto-adjustable Vertical Height of Character : Range 18 63 Character Blinking and Shadowing : Font basis Programmable Symmetrical Row to Row Spacing : Range 0 31 Horizontal Starting Position : 256 different positions (6 dots for each step) Vertical Starting Position : 256 different positions (4 scan line for each step) Scrolling : Effect where 1 character line is scrolled up or down 4 Programmable Window Function and Window Priority Control Selectable Window Shadow Width : H/ V 2, 4, 6 and 8 Dots Supports Background Video Transparency : Font basis or Window basis Full White Pattern Generation for Manufacturing Mode Auto Character Height Control Full-Screen Display RAM Erasing OSD Vertical Bouncing Auto-Detecting & Correction 1 S5D2509 OSD PROCESSOR FOR MONITOR (PRELIMINARY) BLOCK DIAGRAM The OSD Processor consists of 8 blocks on the top level as shown "Figure 1: Functional block diagram". There are 4 input signals for the OSD Processor, which are serial data (SDA), clock (SCL) form a micro controller and sync signals (HFLB and VFLB) from the H/ V sync processor. Through the serial data line, all information for the OSD operation are transferred. Here, the protocol is I2C bus. The data receiver block is a decoder for decoding the serial input data from a micro controller. The serial data is converted to a 16-bit parallel format at the data receiver block. The parallel data are transported to the RAM or registers by the bus line. The internal bus is a kind of star-bus type. Control data comes from the data receiver is used to generate the control signals that control the character size, character position, blank mode, blink mode, background color, and etc, in timing controller and display unit block. All timing signals to read/ write data from/ to the internal RAM and ROM are also generated in the timing controller block. In the PLL block, the internal system clock that is synchronized with HFLB is generated, which is used as a timing reference signal for the OSD processor. SDA SCL 7 Data Receiver (IIC Controller) 8 16 PWM Data 16 RAM Data / 16 Control Data Display RAM (1K-Byte SRAM) ROM Address / 9 Single Color ROM (448X18X12) Multi Color ROM (16X3X18X12) / / PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 9 10 11 PWM Generator 12 13 14 15 16 Frame Control Row Control PWM Register Frame Control Font Control Font Data Font Data 12 12 / / 23 Display Controller 22 Output Stage 21 20 19 H/V/CLK Control H/V/CLK Control INT R_OUT G_OUT B_OUT FBLK Control Register Row Control Display Control HFLB VFLB 6 OSD PLL 17 CLK H-Pulse V-Pulse Timing Controller 2 VCO_IN 3 VREF 4 VICTL 1 VSSA 5 VDDA 18 VSS 24 VDD Figure 1. Functional Block Diagram 2 OSD PRESSOR FOR MONITOR (PRELIMINARY) S5D2509 PIN CONFIGURATIONS Package Type of the S5D2509 is 24-DIP-300. Pin Configuration including PWM Port (9 16 Pin) 8 channels is shown in the figure bellow. VSS_A VCO_IN VREF VICTL VDD_A HFLB SDA SCL PWM0 PWM1 PWM2 PWM3 1 2 3 4 5 6 24 23 22 21 20 19 VDD_D INT R_OUT G_OUT B_OUT FBLK VSS_D VFLB PWM7 PWM6 PWM5 PWM4 S5D2509 7 8 9 10 11 12 18 17 16 15 14 13 Figure 2. Pin configuration 3 S5D2509 OSD PROCESSOR FOR MONITOR (PRELIMINARY) PIN DESCRIPTIONS Table 1. Pin Description Pin No. 1 Signal VSSA Active I/ O Description This pin provides the signal ground to the PLL circuit. We recommend that you separate the analog ground from the digital ground as shown in 'Figure 3 : S5D2509 Application Circuit' (6p) for optimum performance (S5D2509's built-in PLL is sensitive to noise due to wide range PLL characteristics). This voltage is made in an external loop filter and sent to VCO's input block. Operation voltage range is about 1 4V, and you can raise immunity against external noise if you want lower the VCO sensitivity by allowing the max operation voltage range possible at 5V power voltage. Refer to 'PLL Control' (30p). Connect to ground using resistance in order to make the reference current that need to operate internal PLL (PLL region control). Refer to 'PLL Control' (30p)'. PLL gain controlled by controlling VCO Current. This pin supplies +5V supply voltage to the PLL circuit. We recommend that you divide the digital and analog power for PLL as you did in 'Figure 3 : S5D2509 Application Circuit (6p)' to prevent the influence of clock noise on the digital block. 6 7 8 9 10 11 12 13 14 15 16 17 HFLB SDA SCL PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM6 VFLB LOW LOW Input In/ Out In/ Out Output Output Output Output Output Output Output Output Input Horizontal Flyback : This pin is reference signal source of the internal PLL. Serial Data (I2C). We recommend that you use the serial resistor about 1/ 10 value of 5V pull-up resistor as I2C protocol. Serial Clock (I2C). We recommend that you use the serial resistor about 1/ 10 value of 5V pull-up resistor as I2C protocol. PWM DAC0 Output for DC Control other Peripheral. PWM DAC1 Output for DC Control other Peripheral. PWM DAC2 Output for DC Control other Peripheral. PWM DAC3 Output for DC Control other Peripheral. PWM DAC4 Output for DC Control other Peripheral. PWM DAC5 Output for DC Control other Peripheral. PWM DAC6 Output for DC Control other Peripheral. PWM DAC7 Output for DC Control other Peripheral. Vertical Flyback signal : Similar to pin #6, this inputs the negative polarity vertical flyback signal for syncronizing the vertical control circuit. 2 VCO_IN - - 3 VREF - - 4 5 VICTL VDDA - - 4 OSD PRESSOR FOR MONITOR (PRELIMINARY) S5D2509 Table 1. Pin Description (Continued) Pin No. 18 19 Signal VSS FBLK Active I/ O Output Ground for Digital Part Fast Blank Signal : OSD R/ G/ B output is recognized in the PreAMP only when this output pin is high. In other words, if FBLK is low, the OSD R/ G/ B output is not selected in the Pre-AMP. OSD Signal Output (B). OSD Signal Output (G) OSD Signal Output (R) This output pin signifies the color intensity. If you set the intensity control bit to '1' (high) and use with the Pre-AMP supporting intensity function, this pin outputs logic high while the specified character or raster is being displayed. If this pin's output is high, the color level is reduced to half and shows a difference in color level from when it is low, allowing a 16-color choice when this intensity pin and R/ G/ B output are combined. For example, if R, G, B are all high, white is output. If you set the INT bit to '1' (high), the color level becomes reduced to half and outputs gray. +5V Supply Voltage for Digital Part Description 20 21 22 23 B_OUT G_OUT R_OUT INT - Output Output Output Output 24 VDD - Output * In the table above, only HFLB and VFLB's active column is low. This means that HFLB and VFLB are set so that they are inputted as active low in default. For more information, please refer to 'Register Descriptions (13p)'. 5 S5D2509 OSD PROCESSOR FOR MONITOR (PRELIMINARY) APPLICATION CIRCUIT When you are doing PCB Art Work, separate analog VDD and digital VDD. Using PCB pattern, separate analog Ground and main ground, and then connect two ground with Bead as following figure. Because communication noise influences the operation of PLL, I2C communication line keep away from analog block (Pin #1 #5) as possible as. You can improve the monitor's video characteristics (OSD ringing, OSD smear) and regulation characteristics by adding serial resistance to S5D2509's output pins (Pin #19 Pin #23). 5V 103 100u Bead (1uH) 1 39 5.6k 104 2 VSSA VDD 24 VCO_IN INT 23 300 Pre-AMP 12k 3 VREF R_OUT 22 300 Pre-AMP 6.8k Bead (1uH) 100u Analog GND HFLB (5Vpp) 100 103 4 VICTL G_OUT 21 300 Pre-AMP 5 VDDA B_OUT 20 300 Pre-AMP 6 HFLB FBLK 19 300 Pre-AMP S5D2509 SDA (Pull-Up) 7 SDA VSS 18 Main GND VFLB (5Vpp) SCL (Pull-Up) 100 8 SCL VFLB 17 9 PWM0 PWM7 16 10 PWM1 PWM6 15 11 Analog GND Main GND 12 PWM2 PWM5 14 PWM3 PWM4 13 Figure 3 : S5D2509 Application Circuit 6 OSD PRESSOR FOR MONITOR (PRELIMINARY) S5D2509 PACKAGE INFORMATION #24 6.45 + 0.20 0.254 + 0.008 #13 0-15 7.62 0.300 0.2 #1 31.90 MAX 1.256 31.50 + 0.20 1.240 + 0.008 #12 3.81 + 0.20 0.150 + 0.008 (1.95) (0.077) 0.46 + 0.10 0.018 + 0.004 1.27 + 0.10 0.050 + 0.004 2.54 0.100 Figure 4 : S5D2509 Package Information 3.56 + 0.30 0.140 + 0.012 2.51 MIN 0.020 5.08 MAX 0.200 0.0 10 +0 - 0 .10 .05 +0 - 0 .004 .00 2 5 7 S5D2509 OSD PROCESSOR FOR MONITOR (PRELIMINARY) SPECIFICATION ABSOLUTE MAXIMUM RATINGS Table 2. Absolute Maximum Ratings Parameters Supply Voltage Input Voltage Power Dissipation Operating Temperature Range Storage Temperature Range PKG Thermal Resistance : 64.2C / W Symbol VDD VI Pd Topr Tstg Value 0 6.5 0 5.25 1200 -20 70 -40 125 Unit V V mW C C ELECTRICAL CHARACTERISTICS DC Electrical Characteristics Table 3. DC Electrical Characteristics (Ta = 25C, VDD_A = VDD_D = 5V) Parameters (Conditions) Supply Voltage Supply Current (No load on any output) Input Voltage Output Voltage (Iout = 1mA) Input Leakage Current VCO Input Voltage Symbol VDD IDD VIH VIL VOH VOL IIL VVCO Min. 4.75 0.8VDD 0.8VDD -10 Typ. 5.00 2.5 Max. 5.25 25 VSS+0.4 VSS+0.4 10 Unit V mA V V V V uA V 8 OSD PRESSOR FOR MONITOR (PRELIMINARY) S5D2509 OPERATION TIMING OUTPUT SIGNAL R/ G/ B_OUT, INT, FBLK Table 4: Rise/ Fall Time of Output Signal (Ta = 25C, VDDA = VDD=5V, CLOAD = 30pF) Parameters (Conditions) Rise Time Fall Time Symbol tR tF Min. Typ. Max. 2 2 Unit nsec nsec Input Signal HFLB, VFLB Table 5: Frequency of Input Signal Parameters(Conditions) Horizontal Flyback Signal Frequency Vertical Flyback Signal Frequency Symbol fHFLB fVFLB Min. Typ. Max. 120 200 Unit kHz Hz C Interface SDA, SCL Table 6: Operating Time of I2C Interface Parameters (Conditions) SCL Clock Frequency Hold Time for start condition Set Up Time for stop condition Low Duration of clock High Duration of clock Hold Time for data Set Up Time for data Time between 2 access Fall Time of SDA Rise Time of both SCL and SDA Symbol fSCL ths tsus tlow thigh thd tsud tss tfSDA trSDA Min. 500 500 400 400 0 500 500 Typ. Max. 300 20 Unit kHz ns ns ns ns ns ns ns ns ns thd SDA ths SCL thigh tlow tsud Figure 5 : Operation Timing - SDA and SCL 9 S5D2509 OSD PROCESSOR FOR MONITOR (PRELIMINARY) FUNCTIONAL DESCRIPTIONS DATA TRANSMISSION The communication interface between S5D2509 and MCU follows the I2C protocol. As shown in "Figure 6 : Data Transmission Format", It supports two formats to transmit 16-bits register values effectively. After the starting pulse, the transmission takes place in the following order: Slave address with R/ W bit, each 1-byte row/ column address, 2-byte data, and stop condition. An acknowledge signal is received for each byte, excluding only the start/ stop condition. It assigns 8-bits out of 16-bits to font address for selecting character code, because attribute bits of the "Character & Attribute Registers" is composed of 8-bits for convenient adjustment with font unit. By the way, S5D2509 needs 9-bits for addressing 464-fonts by reason that it supports 464-fonts. Therefore, the needed 1-bit is assigned to the RMSB of column address bit pattern as follows "Address Bit Pattern for Display Registers Data". For using the RMSB, it must be enabled the COLEN bit of row address bit pattern. S5D2509's slave address is BAh. It is BBh in read mode, and BAh in write mode. Address Bit Pattern for Display Registers Data (a) Row Address Bit Pattern A15 A14 A13 A12 C4 A11 R3 R3 - R0 : Valid Data for Row Address A10 R2 A9 R1 A8 R0 COLEN X X COLEN : Column Data Format Enable (b) Column Address Bit Pattern A7 A6 A5 X C4 - C0 : Valid Data for Column Address A4 C4 A3 C3 A2 C2 A1 A0 RMSB X RMSB : ROM Address MSB Bit Data Transmission Format C1 C0 'X' : Don't care bit Data format 1: Increment data format START SLAVE A ROW A COLUMN1 A DATA1 A DATA1 A DATA2 A DATA2 A STOP Data format 2: Column data format START SLAVE A ROW A COLUMN1 A DATA1 A DATA1 A COLUMN2 A DATA2 A DATA2 A STOP Figure 6: Data Transmission Formats 10 OSD PRESSOR FOR MONITOR (PRELIMINARY) S5D2509 SDA / SCL Signal at Communication Data Format 1 : Auto Increment Data Format SCL SDA START IIC SLAVE ADDRESS : BA R/W ACK A15 A14 A13 A12 A11 A10 MSB : ROW ADDRESS A9 A8 ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK LSB : COLUMN1 ADDRESS SCL SDA D15 D14 D13 D12 D11 D10 D9 MSB : DATA1 D8 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D15 D14 D13 D12 D11 D10 D9 MSB : DATA2 D8 ACK LSB : DATA1 SCL SDA D7 D6 D5 D4 D3 D2 D1 D0 ACK D15 D14 D13 D12 D11 D10 D9 MSB : DATA3 D8 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK STOP LSB : DATA2 LSB : DATA3 Figure 7 : SDA/ SCL Timing Chart (Format 1) Data Format 2 : Column Data Format SCL SDA START IIC SLAVE ADDRESS : BA R/W ACK A15 A14 A13 A12 A11 A10 A9 MSB : ROW ADDRESS A8 ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK LSB : COLUMN1 ADDRESS SCL SDA D15 D14 D13 D12 D11 D10 D9 MSB : DATA1 D8 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK A15 A14 A13 A12 A11 A10 A9 MSB : COLUMN2 ADDRESS A8 ACK LSB : DATA1 SCL SDA A7 A6 A5 A4 A3 A2 A1 A0 ACK D15 D14 D13 D12 D11 D10 D9 MSB : DATA2 D8 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK STOP LSB : COLUMN2 ADDRESS LSB : DATA2 Figure 8 : SDA/ SCL Timing Chart (Format 2) * As you can see the "Figure 7, 8 : SDA/ SCL Timing Chart", just the time when the SCL is low, the SDA can be occurred transition. Therefore, you must program MCU not to occur timing violation. 11 S5D2509 OSD PROCESSOR FOR MONITOR (PRELIMINARY) MEMORY MAP COLUMN ADDRESS 00 01 02 03 00 01 02 26 27 28 29 CHARACTER & ATTRIBUTE REGISTER [ 30 X 15 DISPLAY RAM ] 12 13 14 00 01 02 15 FF FF TEST REGISTER 15 16 17 FRAME CONTROL REGISTER Figure 9: Memory Map of Display Registers The display RAM's address of the row and column number are assigned in order. The display RAM is composed of 2 register groups (Character & Attribute Register, Frame Control Register). The display area in the monitor screen is 30 columns X 15 rows, so the related "Character & Attribute Registers" are also 30 columns X 15 rows. Each register has a character address and characteristics corresponding to the display location on the screen, and one register is composed of 16-buts. The lower 8-bits and the extended 1-bit (the MSB of row/ column address) are used for selecting a font out of 464 ROM fonts, and upper 8-bits are assigned to give a character attribute to a selected font. "Frame Control Registers" are in the 15th row. "Frame Control Register 0 2" control with frame unit display position of the OSD, height of character, blinking, scrolling, and etc function. "Frame Control Register 3" select extended codes to control 'Blink', 'Shadow', 'Character intensity', and 'Raster intensity'. "Frame Control Register 4" specify the reference value for "Auto height control" and "Row to row space". "Frame Control Register 5 13" control in relation to 4-windows. "Frame Control Register 14 17" are registers for PWM control. Each PWM control register is composed of two channel with 8-bits resolution and control 8 PWM ports. Each register's configurations shown in "Figure 10 : Register Description (13p) ". For more detailed information, refer to "Table 7 : Register Description (14p) ". 12 ROW ADDRESS OSD PRESSOR FOR MONITOR (PRELIMINARY) S5D2509 REGISTER DESCRIPTION Character & Attribute Register : Row 00 - 14, Column 00 - 29 F Blink CTL1 E SHA CTL0 D RB C RG B RR A CB 9 CG 8 CR 7 C7 6 C6 5 C5 4 C4 3 C3 2 C2 1 C1 0 C0 Extended Code Raster Color Character Color Character Code (256 Font Address) Frame Control Register 0 : Row 15, Column 00 F E D C B - - - - - A 9 8 7 6 5 4 3 PFEN AutoH FullW ExEN BGEN ScrEN ScrT BliEN 2 BliT 1 Erase 0 EN Frame Control Register 1 : Row 15, Column 01 F CP2 E CP1 D CP0 C HF2 B HF1 A 9 8 7 6 5 HF0 DOT1 DOT0 HPOL VPOL CH5 Polarity 4 CH4 3 CH3 2 CH2 1 CH1 0 CH0 PLL Control Character Height Control Frame Control Register 2 : Row 15, Column 02 F HP7 E HP6 D HP5 C HP4 B HP3 A HP2 9 HP1 8 HP0 7 VP7 6 VP6 5 VP5 4 VP4 3 VP3 2 VP2 1 VP1 0 VP0 Horizontal Start Position Vertical Start Position Frame Control Register 3 : Row 15, Column 03 F Blink E SHA D C B RINT CINT Blink A SHA 9 8 7 RINT CINT Blink 6 SHA 5 4 3 RINT CINT Blink 2 1 0 SHA RINT CINT CTL00 CTL11 CTL10 CTL01 Frame Control Register 4 : Row 15, Column 04 F E D C B A 9 8 7 6 5 - - AREF5 AREF4 AREF3 AREF2 AREF1 AREF0 - - - 4 RS4 3 RS3 2 RS2 1 RS1 0 RS0 Auto Height CTL Reference No Row Space Frame Control Register 5, 7, 9, 11 : Row 15, Column 05, 07, 09, 11 F E D C B A 9 8 7 WIN_I WIN_B WIN_G WIN_R RSTR3 RSTR2 RSTR1 RSTR0 HW1 6 5 HW0 VW1 Shadow Width 4 3 2 1 0 VW0 REND3 REND2 REND1 REND0 Window End Row Address Window Color Window Start Row Address Frame Control Register 6, 8, 10,12 : Row 15, Column 06, 08, 10, 12 F WEN E D C B A 9 8 7 6 5 4 3 2 1 0 - - CSTR4 CSTR3 CSTR2 CSTR1 CSTR0 WSHA - - CEND4 CEND3 CEND2 CEND1 CEND0 Window Start Column Address Window End Column Address Frame Control Register 13 : Row 15, Column 13 F E D C B A 9 8 7 6 5 4 3 2 1 0 - - WPR31 WPR30 - - WPR21 WPR20 - - WPR11 WPR10 - - WPR01 WPR00 Window Priority 3 Window Priority 2 Window Priority 1 Window Priority 0 Frame Control Register 14 ~ 17 : Row 15, Column 14 ~ 17 F E D C B A 9 8 7 6 5 4 3 2 1 0 PWM7 PWM6 PWM5 PWM4 PWM3 PWM2 PWM1 PWM0 PWM7 PWM6 PWM5 PWM4 PWM3 PWM2 PWM1 PWM0 PWM1 / PWM3 / PWM5 / PWM7 PWM0 / PWM2 / PWM4/ PWM6 Figure 10: Register Description 13 S5D2509 OSD PROCESSOR FOR MONITOR (PRELIMINARY) Table 7: Register Description Registers Character & Attribute Registers (Row 00 14, Column 00 29) Bits Blink (Bit F) Description Character Blink Set this bit to activate character blinking effect or use as 'CTL1' bit for selecting "Extended code set". Character Shadow Set this bit to activate character shadowing effect or use as 'CTL0' bit for selecting "Extended code set". Raster Color A color out of 16-colors is selected by these 3-bits and 'RINT' bit in "Frame Control Register 3" as raster color. Character Color A color out of 16-colors is selected by these 3-bits and 'CINT' bit in "Frame Control Register 3" as character color. Character Code Address These 8-bits is used for accessing 256 ROM fonts. If you access over 256 FOM fonts, Column data format must be used. Column address MSB 'RMSB' bit is used for MSB of 9-bits ROM fonts address. Reserved. Programmable Full White Pattern Enable As size as you want, you can determine full white pattern by using "Window size" at 320 OSD resolution. On the other hand, 'FullW' bit is used automatic "Full white pattern generation". Auto Adjustable Vertical Font Height Control If this bit is high, height of font is sustained as 'AREF' Bits regardless of video input mode. Full White Pattern Generation If this bit is set high, OSD outputs full white pattern automatically. Extended Code Enable If this bit is set high, Bit F/ E in "Character & Attribute Registers" are used for selecting extended code set 'CTL00 CTL11'. Back Ground Enable If you set this bit to '1', black color of OSD raster area is transparent. This control bit is aimed for round-type OSD window generation. Scroll Enable Refer to 'Scrolling (28p)'. Scroll Time Control If this bit is '1', the scroll time is 0.5sec, otherwise 1.0sec. Blink Enable If you set this bit to high, blink the font with 'Blink' attribute. Blink Time Control If this bit is '1', the blink time is 0.5sec, otherwise 1.0sec. RAM Erasing RAM data are erased by setting this bit. Refer to 'Display RAM (19p)'. OSD Enable The character display is controlled by this bit. If this bit is high, OSD is enable. Otherwise, disable. When this bit is disabled, OSD isn't output inspite of writing control data. SHA (Bit E) RB, RG ,RR (Bit D B) CB, CG, CR (Bit A 8) C7 C0 (Bit 7 0) Frame Control Registers-0 (Row15, Bit F B PFEN (Bit A) Column00) AutoH (Bit 9) FullW (Bit 8) ExEN (Bit 7) BGEN (Bit 6) Scrl (Bit 5) ScrT (Bit 4) BliEN (Bit 3) BliT (Bit 2) Erase (Bit 1) EN (Bit 0) 14 OSD PRESSOR FOR MONITOR (PRELIMINARY) S5D2509 Table 7: Register Description (Continued) Registers Frame Control Registers-1 (Row15, Column01) Description CP2 CP0 Charge Pump Output Current Control (Bit F D) This is the PLL block's internal phase detector output status, converted into current. The output is determined by these 3-bits. CP2 0 0 0 0 HF2 HF0 (Bit C A) CP1 0 0 1 1 CP0 0 1 0 1 80A 120A Current 40A CP2 1 1 1 1 CP1 0 0 1 1 CP0 0 1 0 1 Current 160A 200A 240A 280A Bits Horizontal Frequency PLL's horizontal frequency is decided by the combination of these 3-bits. This is related to the selection of DOT[1:0], so you can't numerically express the frequency range with only the HF[2:0] selection. For more information, please refer to 'Separating region of frequency (31p)'. Resolution Control (Dots/ Line) Dot1 0 0 1 1 dot0 0 1 0 1 No. Of Dots 640 dots/line 800 dots/line 1024 dots/line 1280 dots/line DOT1, DOT0 (Bit 9,8) As shown above, the number of dots per horizontal line is decided by a combination of these two bits. HPOL (Bit 7) Polarity of Horizontal Fly Back Signal If this bit is '1', HFLB's polarity is positive, and if '0', it is negative. In other words, this bit is set to '1' if active high, and '0' if active low. Polarity of Vertical Fly Back Signal If this bit is '1', VFLB's polarity is positive, and if '0', it is negative. In other words, this bit is set to '1' if active high, and '0' if active low. Character Height Control The purpose of CH[5:0] is to output OSD of a uniform size even if the resolution changes. If you adjust the value in the range of CH = 18 CH = 63, each line's repeating number is decided (standard height CH = 18 is the reference value), by which the line is repeated. For more information on repeating number selection, refer to 'Character Height (26p)'. Vertical Start Position Control (= VP[7:0] x 4) Signifies top margin height from the V-Sync reference edge. VPOL (Bit 6) CH5 CH0 (Bit 5 0) Frame Control Registers-2 (Row15, Column02) VP7 VP0 HP7 HP0 Horizontal Start Position Control ( = HP[7:0] x 6) Signifies delay of the horizontal display from the H-Sync reference edge to the character's 1st pixel location. * The purpose of bits 'HPOL', and 'VPOL' is to provide flexibility when using the S5D2509 IC. No matter which polarity you choose for the input signal, the IC will handle them identically, so you can select active high or active low according to your convenience. 15 S5D2509 OSD PROCESSOR FOR MONITOR (PRELIMINARY) Table 7: Register Description (Continued) Registers Frame Control Registers-3 (Row15, Column03) Bits CTL11 (Bit F C) Description Extended Code Set 11 If 'ExEN' bit of "Frame Control Register 0" is set to high, when Bit F (CTL1) and Bit E (CTL0) of "Character & Attribute Registers" are set to '11', these extended code set is referred as the combination of 'Blink', 'SHA', 'RINT', and 'CINT'. That is, you may set previously the combination that you want. and then select the extended code set by 'CTL1' and 'CTL0' bits. Extended Code Set 10 If 'ExEN' bit of "Frame Control Register 0" is set to high, when Bit F (CTL1) and Bit E (CTL0) of "Character & Attribute Registers" are set to '10', these extended code set is referred as the combination of 'Blink', 'SHA', 'RINT', and 'CINT'. That is, you may set previously the combination that you want. and then select the extended code set by 'CTL1' and 'CTL0' bits. Extended Code Set 01 If 'ExEN' bit of "Frame Control Register 0" is set to high, when Bit F (CTL1) and Bit E (CTL0) of "Character & Attribute Registers" are set to '01', these extended code set is referred as the combination of 'Blink', 'SHA', 'RINT', and 'CINT'. That is, you may set previously the combination that you want. and then select the extended code set by 'CTL1' and 'CTL0' bits. Extended Code Set 00 If 'ExEN' bit of "Frame Control Register 0" is set to high, when Bit F (CTL1) and Bit E (CTL0) of "Character & Attribute Registers" are set to '00', these extended code set is referred as the combination of 'Blink', 'SHA', 'RINT', and 'CINT'. That is, you may set previously the combination that you want. and then select the extended code set by 'CTL1' and 'CTL0' bits. Reserved. Auto Height Control Reference Number If 'AutoH' bit of "Frame Control Register 0" is set to '1', must set these AREF[5:0] from 1 to 63. These control bits means the number of font that you want to display in direction of vertical monitor line. In this case, that is, 'AutoH' bit is set to '1' and AREF[5:0] bits is set, OSD fonts sustain constant vertical height regardless of video input mode change. If calculated font height is smaller than 18, font height is displayed by 18 lines. In other hands, if 'AutoH' Bit is set to '0', this function is ignored and character height is determined by CH[5:0] of "Frame Control Register 1". Refer to 'Character Height (26p)'. Reserved. CTL10 (Bit B 8) CTL01 (Bit 7 4) (Bit 3 0) Bit F E Frame Control Registers-4 (Row15, Column04) AREF (Bit D 8) Bit 7 5 RS (Bit 4 0) Row Space Number It means the line number between a character row and the next row. The default value is 0. For obtaining symmetrical row space, first and last line are extended in each row. (line number for spacing = RS[4:0] 2) Refer to 'Figure 15 : OSD window area(24p)'. 16 OSD PRESSOR FOR MONITOR (PRELIMINARY) S5D2509 Table 7: Register Description (Continued) Registers Frame Control Registers-5, 7, 9, 11 Bits WIN_I, WIN_B, WIN_G, WIN_R (Bit F C) RSTR3 RSTR0 (Bit B 8) HW1,HW0 (Bit 7 6) VW1,VW0 (Bit 5 4) REND3 REND0 (Bit 3 0) Registers-6, 8, 10, 12 (Row15, Column06, 08, 10, 12) Bit E D CSTR4 CSTR0 (Bit C 8) WSHA (Bit 7) Bit 6 5 CEND4 CEND0 (Bit 3 0) Description Window Raster Color Attribute The priority of raster color is determined by these bits is higher than raster color is determined by RB/ RG/ RR bits of "Character & Attribute Registers". 'WIN_I' bit may make 16-colors with the preAMP that support intensity function as like as 'CINT' or 'RINT'. Window Start Row Address : Range 0 15 It means the row address that window starts from. About actually start point, refer to 'III-6.3 Window Generation'(27p). Horizontal Width of Window Shadowing The horizontal width of window shadow is determined by these HW[1:0] bits setting as follows : (Horizontal Width = HW 2 Dots) Vertical Width of Window Shadowing The vertical width of window shadow is determined by these VW[1:0] bits setting as follows : (Vertical Width = VW x 2 Lines) Window End Row Address : Range 0 15 It means the row address that window stops on. About actually stop point, refer to 'III-6.3 Window Generation'(27p). Reserved. Window Start Column Address : Range 0 29 It means the column address that window starts from. About actually start point, refer to 'III-6.3 Window Generation'(27p). Window Shadowing Enable If this bit is set '1', activate the area of window shadow as width as HW and VW. Reserved. Window End Column Address : Range 0 29 It means the column address that window stops on. About actually stop point, refer to 'III-6.3 Window Generation'(27p). (Row15, Column05, 07, 09, 11) Frame Control WIN_EN (Bit F) Window Enable Set this bit to activate window. * That "Frame Control Register 5" pair with "Frame Control Register 6" control the function about window. As like above, that the odd register pair with the even register in "Frame Control Register 7 12" control about each "Window 1 3". 17 S5D2509 OSD PROCESSOR FOR MONITOR (PRELIMINARY) Table 7: Register Description (Continued) Registers Frame Control Registers-13 (Row15, Column13) Bits Bit F E WPR31, WPR30 (Bit D C) Bit B A WPR21, WPR20 (Bit 9 8) Bit 7 6 WPR11, WPR10 (Bit 5 4) Bit 3 2 WPR01, WPR00 (Bit 1 0) Frame Control Registers-14 17 (Row15, Column1417) PWM7 PWM0 (Bit 7 0) PWM Port Control (Even) Decides channel 1/ 3/ 5/ 7 PWM's output duty cycle and waveform. PWM7 PWM0 (Bit F 8) Reserved. Window Priority 3 Determine a window out of 4 windows that has the lowest priority. The selected window area may be overlapped by a area of the window that has higher priority. Reserved. Window Priority 2 Determine a window out of 4 windows that has the 3rd priority. Reserved. Window Priority 1 Determine a window out of 4 windows that has the 3rd priority. Reserved. Window Priority 0 Determine a window out of 4 windows that has the highest priority. The selected window area overlaps lower priority windows. PWM Port Control (Odd) Decides channel 2/ 4/ 6/ 8 PWM's output duty cycle and waveform. Description * If you determine window priorities with "Frame Control Register 13", each window overlaps lower priority windows. So you can make pop-up window OSD. Refer to 'Transparency (23p)'. 18 OSD PRESSOR FOR MONITOR (PRELIMINARY) S5D2509 ADDRESSING DISPLAY RAM 1 k-Byte SRAM (512 x 16 bits) is built in S5D2509. Registers are distributed within 16 rows x 30 columns. But, for facilitating internal caculation, addressing is done using exponents of 2, and the S5D2509 is composed of 16 rows x 32 columns RAM Cell. if 'Erase' Bit of "Frame Control Register 0" is enabled by setting '1' and erased RAM, 480 RAM cells are erased excepting only 16th row (Frame Control Registers). Therefore, the 'Erasing Time' is measured with 480 RAM cells as the standard. * Erasing Time Erasing Time = RAM Clock x 480 (RAM Cell volume) RAM Clock = 12 dot clock Dot Clock = 1/ (dot frequency) Dot Frequency = Horizontal Frequency x Resolution (mode) So, the maximum value of the 'Erasing Time' is as follows. (Erasing Time) MAX = (12 x 480) / (30k x 640) = 30ms When you are programming with MCU, you have not to give the S5D2509 other operation or command during the (Erasing Time)MAX at a minimum, if you hope that timing violation isn't happened. ROM FONTS S5D2509 provides 464 ROM fonts for displaying OSD icons, which allows the use of multi-language OSD icons. Out of the 464 ROM fonts, 448 are standard fonts, and 16 are multi-color fonts. The standard font is placed at 000h address is reserved for blank data. Each multi-color font is composed of 4 color attribute ROM fonts are as shown "Figure III-4.2 : Composition of ROM Fonts". A multi-color font is made by 'OR operating with these 3 fonts. When you want to access this multi-color font, you may call the address of R-color attribute font. In example, the addresses of 1C0h, 1D0h and 1E0h mean respectively R, G, B color attribute fonts. and that the multi-color font is accessed by addressing 1C0h is made with 1C0h, 1D0h, and 1E0h through 'OR' operation. To do addressing 464 ROM fonts, as explained at "Memory Map (12p)", the S5D2509 uses 9 bits added 1 extended bit which use the MSB of row/ column address and 8 bits for character code bits in "Character & Attribute Registers". 19 S5D2509 OSD PROCESSOR FOR MONITOR (PRELIMINARY) 0 00 000h 1 001h E 00Eh F 00Fh 01 010h 011h 01Eh 01Fh Single-Color Fonts 1A 1A0h 1A1h 1AEh 1AFh 1B 1B0h 1B1h 1BEh 1BFh 1C 1C0h 1C1h 1CEh 1CFh Multi-Color Fonts 1E0h : B 1D0h : G 1C0h : R Figure 11: Composition of ROM Fonts Notes for when making S5D2509 Fonts Address 000h is appointed as blank data. RAM's initial values are all 0, and all bits are written as 0 when you erase the RAM, so blank data means the initial value. In other words, blank data means 'do nothing'. You don't need to write any data for the space font, except for 000h. It just needs to be an undotted area. If you want to express a font image color the way you want according to the multi-color font characteristics, you must keep in mind that you are using a multi-color font when selecting the character or raster color. When you select a character or raster color, the color that was 'OR' operation to the original color is expressed. You should also consider the multi-color font's raster part. Since raster color is applied to '0' areas even with 'OR' operation, you can express many different background colors even with one multi-color font. The best thing to do is to set any part that you don't want to change color as the character part, and the changeable parts as the raster part when using a multi-color font. 20 OSD PRESSOR FOR MONITOR (PRELIMINARY) S5D2509 COLORING If you have an intensity feature, the number of possible colors you can express becomes doubled. In other words, the number of colors you can represent with three colors blue, green, and red is 8 (= 23), but with the intensity feature, it is 16 (= 24). Character Color Character Color is assigned for each font, and the 4 components for expressing a color are listed below. Blue Green Red Intensity CB bit [A] of "Character & Attribute Registers" CG bit [9] of "Character & Attribute Registers" CR bit [8] of "Character & Attribute Registers" CINT bit of extended code set in "Frame Control Register 3" which is set by CTL1:CTL0 bits [F:E] in "Character & Attribute Registers". Raster Color Blue Green Red Intensity RB bit [D] of "Character & Attribute Registers" RG bit [C] of "Character & Attribute Registers" RR bit [B] of "Character & Attribute Registers" RINT bit of extended code set in "Frame Control Register 3" which is set by CTL1:CTL0 bits [F:E] in "Character & Attribute Registers". If the extended code is enabled by setting ExEN bit in "Frame Control Register 0" to '1', that the extended code is set in "Frame Control Register 3" is selected by [F:E] bits of "Character & Attribute Registers". So, you can select attribute with font unit by the various composition of Blink, Shadow, Raster Color Intensity, and Character Color Intensity. Otherwise, you can select just blink and shadow attributes with font base. Therefore, if you want to express 16 colors, you must enable ExEN bit and also set RINT and CINT bits of extended code set in "Frame Control Register 3" to '1'. Multi-Color Font The multi-color fonts supported in S5D2509 is composed of 3 fonts (red, green, and blue) as the structure in "III4.2 ROM Fonts"(21p) and can express 16 colors as single-color fonts is did 'OR' operation. The reason for using such multi-color fonts is that it makes it possible to express different colors within one font. Therefore, if one font's character, symbol and background (raster) are each composed of a single color, you don't need to use a multi-color font. Let's take a look at an example. When making a single-color font, the dots make up a font's character or symbol, and the other undotted areas are called raster (background without character or symbol). If we think of this in a binary format, the dotted areas are '1', and the undotted areas are '0'. If we decide upon a character color, it will only influence the areas that are '1', and if you select a raster color, it will only influence the areas that are '0'. For example, in the standard font file, the font of 020h doesn't have any part that is '1'. So even if you select a character color for this font, there will be no changes since there are no '1' areas. But if you select a raster color for this font, since all areas are '0', the entire font area will become the selected raster color. 21 S5D2509 OSD PROCESSOR FOR MONITOR (PRELIMINARY) We do 'OR' operation for the 3 fonts after masking IC that express red/ green/ blue to make one font (multicolor). In other words, when making a multi-color font using a font editor, the 3 fonts are handled as separated fonts before they are combined, but when the combination is done and used in programming or in an actual display, it is handled as one font. The '1' area of the multi-color font is influenced by the character color selection, and the '0' area is influenced by the raster color selection. That is, if you call the address of R-color attribute font, the '1' area of R/ G/ B color attribute fonts in the left side combined and the font did 'OR' operation in the right side is displayed as shown in following figure. B B B B 1 1 0 R Y G C 1C0h : Red B 1D0h : Green 1F0h : Blue Masked data of mulit-color font : 1C0h Displayed font : 1C0h B Figure 12 : Multi-Color Font's composition 22 OSD PRESSOR FOR MONITOR (PRELIMINARY) S5D2509 Transparency If BGEN bit of "Frame Control Register 0" is enabled, the part that raster color is a black within OSD becomes transparent, and video displayes at the part of OSD raster. Therefore, if you use this bit, you can make OSD window various OSD shapes with perfect freedom, which the shapes are not only rectangle but also rounded rectangle, circle, or etc. That is, when you design fonts, at first design OSD, and then make fonts to include character in designed OSD window as like the character part of fonts indicated 1 and 2 in "Figure 13 : Various OSD window by setting BGEN bit", and then set raster color of the fonts to black, and then enable BGEN bit, in the long run, you can express various OSD shapes. At this time, if you set shadow attribute, raster part of the fonts that enabled back ground enabled by BGEN bit is the area except character part and shadowed area as like "Figure 14 : The part influenced by BGEN bit". 1 2 Figure 13 : Various OSD window by setting BGEN Bit Red s Blue s s Blue Green Character Red Shadow Raster Figure 14: The part influenced by BGEN Bit 23 S5D2509 OSD PROCESSOR FOR MONITOR (PRELIMINARY) SIZING / POSITIONING Window Shadow Horizontal Width Window Start Position Row Row Space Font Height Row Space Window Shadow Vertical Width Window Stop Position Figure 15 : OSD window area Positioning The "Frame Control Register 2"'s HP[F:8] bits signify delay of the horizontal display from the H-Sync reference edge to the character's 1st pixel location, and is controlled by multiplying HP[F:8]'s range value by 6. Also, VP[7:0] bits signify the top margin height from the V-Sync reference edge, and is controlled by multiplying 4 to the VP[7:0]'s range value. Therefore, it is "HP x 6 = 256 x 6 = 1536, VP x 4 = 256 x 4 = 1024" that correspond to the maximum resolution (1600 x 1200 mode) of the current monitor. Whereas VP and HP explained above set the initial reference point of the OSD display area (15 rows x 30 columns), As like "Figure III-6 : OSD window area", RSTR, CSTR, REND and CEND bits in "Frame Control Register 5 12" decide each window area from the left-top point of OSD display area. But RSTR and REND are controlled by 4 bits, they have a range 0 14 actually because window area is within OSD display area. In the same reason, CSTR and CEND are controlled by 5 bits, but they have a range 0 29. 24 OSD PRESSOR FOR MONITOR (PRELIMINARY) S5D2509 (HFLB) VP [7:0] HP [7:0] OSD characters 30 columns (= 30 x 12 dots) 15 rows (= 15 x 18 dots) Background Screen (VFLB) Figure 16: Frame Composition with the OSD Characters Windows shadow width HW and VW bits in "Frame Control Register 5, 7, 9, 11" mean each horizontal and vertical width of window shadow as shown in "Figure 15 : OSD window area". The actual value is calculated by (HW x 2 Dots) and (VW x 2 Lines). Shadow color is set by only black for the characteristics of shadowing. Also, it can display not only OSD area (15 rows x 30 columns) but also the extended area by window shadow. That is, to use window shadow function, you may not construct the window less than the maximum OSD area. Window Generation As shown in "Figure III-6 : OSD window area", window size is determined by setting CSTR, RSTR, CEND, and REND bits, which mean as a address with font unit in window area. The actual and physical start point of window is the left-top point of the font area indicated 'Window Start Position' in "Figure 15 : OSD window area". Also, the actual stop point of window is the right-bottom point of the font area indicated 'Window Stop Point'. If 'WEN' bit in each window is enabled by setting to high, the window generated as above is displayed with the window priority determined by 'WPR' bits in "Frame Control Register 13". 25 S5D2509 OSD PROCESSOR FOR MONITOR (PRELIMINARY) Character Height The purpose of CH[5:0] (Character Height) is to output a uniformly sized OSD even if the resolution changes. To express a character height of CH = 18 CH = 63 after receiving CH[5:0]'s input from the "Frame Control Register 1", decide on each line's repeating number(standard height CH = 18) and repeat the lines. The following figure shows two examples of a height-controlled character. Height control is control is carried out by repeating some of the lines. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 : added line Standard Font (12*18) Standard Font inhigh vertical resoultion 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Height-controlled font : added line Standard Font (12*18) Standard Font in more higher vertical resoultion Height-controlled font Figure 17: Character Height Control Repeating line-number can be found by the following formula. [# of the repeating lines = 2 + N x M ] , where N = 1, 2, 3, ... and M = round { 14 / ( CH[5:0] - 18 ) }. (i) If CH[5:0] is greater than 32 and less than or equal to 46 (32 < CH[5:0] 46), all lines are repeated once or twice. The lines that are repeated twice are chosen by the following formula. where N = 1, 2, 3, ... and M = round { 14 / ( CH[5:0] - 32 ) }. 26 OSD PRESSOR FOR MONITOR (PRELIMINARY) S5D2509 (ii) If CH[5:0] is greater than 46 and less than or equal to 60 (46 < CH[5:0] 60), all lines are repeated tow or three times. The lines that are repeated three times are chosen by the following formula. where N = 1, 2, 3, ... and M = round { 14 / ( CH[5:0] - 46 ) }. (iii) If CH[5:0] is greater than 60 and less than or equal to 64 (60 < CH[5:0] 64), all lines are repeated three or four times. The lines that are repeated four times are chosen by the following formula. where N = 1, 2, 3, ... and M = round { 14 / ( CH[5:0] - 60 ) }. CH's reference value is 18, and even if you input 0, it operates in the same way as when CH=18. The repeating line-number is limited to 16. If the M value is less than or equal to 1, all lines of the standard font are repeated more than once. Auto Height Control function is executed by enabling 'AutoH' bit in "Frame Control Register 0" and setting the number of OSD fonts that you need vertically at 'AREF' bits in "Frame Control Register 4". At this time, the reason of that 'AREF' are 6 bits is as follows : At first, we suppose that the maximum of vertical resolution is 1200 lines on Monitor. In case that the minimum of font height is 18 lines, the number of OSD font is vertically 67 (=1200/ 18). Therefore, it is satisfied that 'Auto Height Control Reference Number' is 63 (=26). That is, if you enable 'AutoH' bit and set 20 to 'AREF' bits, height lines in a font is determined to display 20 fonts vertically at maximum resolution as shown in the figure below, and the same size of OSD display regardless of changing resolution. If the font height calculated by AREF value is less than 18 lines, the font height displayes as many as 18 lines. 1 Monitor Display Area 20 OSD Fonts Figure 18 : Auto Height control Auto Height Control Reference Number = 20 27 S5D2509 OSD PROCESSOR FOR MONITOR (PRELIMINARY) VISUAL EFFECT Shadowing Character 'R' Font appear the effect shown in figure below by character shadowing. the principle that 1 pixel to the right, below, and diagonal below the character makes black. C S S S Shadowing Figure 19 : Character Shadowing As shown in "Figure 15 : OSD window area" , windows shadowing is started after delay as much as, "VW" and "HW". Window shadow is also composed of block as like as character shadow. Scrolling Scrolling is slowly displaying or erasing a character from the top line to the bottom. This effect makes it look as if 1 character line is scrolling up or down. However, you must remember that scrolling is on/ off only when OSD is enabled/ disabled. Figure 20 : Scrolling 28 OSD PRESSOR FOR MONITOR (PRELIMINARY) S5D2509 PWM CONTROL PWM control is used for DC controlling the peripheral. The PWM generation block uses the input duty to output a pulse of "Duty / 256", with H_SYNC are reference. fPWM Internal reference pulse PWM OUTPUT 00100000 01000000 01100000 Figure 21: fPWM Timing Chart The PWM signal's frequency (fPWM) changes according to the horizontal flyback signal frequency and the horizontal mode (320 dots/ line, ...), as shown in the table below. The PWM clock is selected by using the 'HF' and 'DOT' bits of "Frame Control Register 1". That is, to correspond the frequency to each resolution mode, the PWM clock is selected by using the system clock as shown in the table. Table 8 : PWM clock value each mode 640 Dots / Line PWM Clock System Clock * 2 800 Dots / Line System Clock * 3 1024 Dots / Line System Clock * 4 1280 Dots / Line System Clock * 5 Range of fPWM (frequency of PWM) is separated as shown below, and the fPWM is generated by different formula each other as shown in below table, to output the average value in according to the region. Table 9 : fPWM value each mode 640 Dots / Line fPWM (640 / 512) * fH 800 Dots / Line (800 / 768) * fH 1024 Dots / Line fH 1280 Dots / Line fH 29 S5D2509 OSD PROCESSOR FOR MONITOR (PRELIMINARY) PLL CONTROL PLL (Phase Lock Loop) is feedback controlled circuit that maintains a constant phase difference between a reference signal and an oscillator output signal. The PLL of S5D2509 is charge-pump PLL , and is generally composed PFD, charge pump, VCO, and Divider. To support VGA UXGA grade, divider has the ratio of 640/ 800/ 1024/ 1280, and the range of the HFLB input frequency for reference is 30kHz 120kHz. At this time, needed the output frequency of VCO is 19.2 MHz 153.6MHz. H/ W and S/ W setting is needed for optimal operation of PLL. The application circuit of Pin #2 and Pin #3 is representative of H/ W setting. CP, FHF, and DOT bits in "Frame Control Register 1" is representative of S/ W setting. You had better set the tuning factor explained above by referring to the following reference. Locking Range As you can see the figure below, it is 2.5V that measured voltage at Pin #2 to optimize OSD quality. Also, locking voltage range of PLL is 1.0V 4.0V, and the proper voltage range of PLL to capture well is 1.7V 3.3V. 4.0V fMax Ve(max) 3.3V 1.5V 2.5V 1.5V 1.7V Ve(min) fC (Capture) fO 1.0V fL (Locking) Figure 22 : PLL Locking Range 30 OSD PRESSOR FOR MONITOR (PRELIMINARY) S5D2509 Separating region of frequency To reduce influence of the noise that exist in VCO input voltage, because it is desirable that VCO gain is small, each region of frequency is separated in 2 5 EA. Each region is overlapped for thermal characteristics and parameter variation in a process of manufacture. VCO_IN 4V 71.8 98.1 138.7 152.8 170.4 1V 11.0 54.2 73.1 107.1 127.0 VCO_OUT 150MHz 200MHz 50MHz 100MHz Figure 23 : PLL frequency range (Type 1) VCO_IN 4V 71.8 98.1 166.7 1V 11.0 54.2 73.4 VCO_OUT 150MHz 200MHz 50MHz 100MHz Figure 24 : PLL frequency range (Type 2) VCO_IN 4V 71.8 162.1 1V 11.0 54.2 VCO_OUT 100MHz 150MHz 200MHz 50MHz Figure 25: PLL frequency range (Type 3) 31 S5D2509 OSD PROCESSOR FOR MONITOR (PRELIMINARY) Separation of frequency region is in need of the multifarious consideration about PLL tuning factors as explained before. HF bits in "Frame Control Register 1" are not selecting from out of 8 (23)steps uniformly, but selecting 3 types shown in table delow as you can see "9.2 Separating region of frequency". In 'Type 1', HF2/HF1/HF0 bits are setting each 0/0/0, 0/0/1, 0/1/0, 0/1/1, 1/0/0 (1/0/1), in 'Type 2' 0/0/0, 1/1/1, and in 'Type 3' 0/0/0, 0/0/1, 1/1/0. HF2 0 0 0 0 1 1 1 HF1 0 0 1 1 0 0 1 HF0 0 1 0 1 0 1 0 90 MHz Fdot < 160 MHz PLL Dot Frequency Range 19.2 MHz < Fdot < 70 MHz 70 MHz Fdot < 90 MHz 90 MHz Fdot < 128 MHz 128 MHz Fdot < 140 MHz 140 MHz Fdot < 160 MHz 1 1 1 70 MHz Fdot < 160 MHz After fixing time constants of the external circuit and PLL control bits except HF bits, if HF bits are stepped up, the voltage measured at Pin #2 drops. On the contrary, if HF bits are stepped down, the voltage rises. The voltage measured at Pin #2 don't change by changing CP bits. As changing the external register in Pin #3, the range is shiftted without changing slope in the figures shown before about 'PLL frequency region'. In other words, if the value of the external register in Pin #3 rises, the voltage measured at Pin #2 (VCO_IN) is shiftted upward without changing slope shown in figures before. If the external register in Pin #4, the slope is changed without shifting shown in figures before. That is, if the value of the external register in Pin #4 rises, the slope shown in figures before rises. After initial setting refferred to the table below in the side view of S/W and the figure "S5D2509 Application Circuit" in the side view of H/W. Range 30kHz 40kHz 40kHz 50kHz 50kHz 70kHz 70kHz 110kHz 110kHz 120kHz CP2 0 1 1 1 1 CP1 1 0 1 1 1 CP0 1 1 1 1 1 HF2 0 0 0 0 0 HF1 0 0 0 1 1 HF0 0 0 1 0 1 DOT1 DOT0 1 1 1 1 1 1 1 1 1 1 Hexa 63h A3h E7h EBh EFh V (Pin #2) 2.18V 2.68V 2.68V 3.16V 1.34V 2.64V 1.42V 3.10V 1.92V 2.44V Table 10: Recommand setting of PLL control bits 32 |
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